5G wireless networks will support 1,000-fold gains in capacity, connections for at least 100 billion devices and a 10Gbps individual user experience capable of extremely low latency and response times. To meet the security requirements that go along with this next evolution in mobile networks, Cavium is demonstrating its single-chip OCTEON III processor, which runs a full IPsec security application at 100Gbps throughput.
By 2019, global mobile IP traffic will reach an annual run rate of 292 exabytes, up from 30 exabytes in 2014, according to Cisco’s Visual Networking Index. Global network users will generate 3 trillion Internet video minutes per month—the equivalent of 6 million years of video, 1.2 million video minutes every second, or more than two years’ worth of video every second. At the same time, secure transport throughput requirements in wireless networks are growing exponentially, creating the need for much higher performance processors with advanced security acceleration in next-generation equipment.
The Cavium OCTEON III 48-core 64-bit CN78xx processor is designed to power a variety of network components, including the mobility management entity (MME), serving gateways (SGW) and packet data network gateways (PGW), providing a 2.5X increase over previously-available performance levels and offering close to bare-metal silicon performance while utilizing standard software OpenDataPlane (ODP) APIs.
Cavium has worked closely with Linaro to support the new ODP initiative and has expanded support for it to the OCTEON III processor line as well as the ThunderX family of processors.
“OpenDataPlane will allow Cavium customers to run their dataplane applications on a wide range of our processors,” said Raghib Hussain, Corporate VP/GM and CTO. “The ability to write applications once and then use them on many different processors and architectures is very appealing and since it is backed by a true open standards body, customers will not be locked into legacy architectures.”